FPGA Design & Verification (Staff/Senior Staff Engineer)

Permanent
  • Post Date: 2020-09-23
  • Apply Before: 2020-10-23
  • Job Level: Executive - Senior
  • Min Year of Experience: 6
  • Min Qualification: Bachelor Degree
  • Based In: Bayan Lepas, Penang
Job Description
FPGA Design and Verification Engineer to develop volatile and non-volatile memory sub-system and algorithm with specific custom logic for ARM CPU based MCU platform. As memories are changing, memory subsystem design is also going through changes in its feature set, bus protocols, interoperability and frequency requirements. The ideal candidate for this role must be versatile, dynamic and self-driven who can offer innovative ideas and solutions for FPGA based system design for prototyping and testing of embedded and external memory device.


Responsibilities

  • Develop memory subsystem based on AHB or AXI interconnect protocol using Verilog/System Verilog.
  • Develop high speed serial interfaces with SDR and DDR protocol using FPGA resources.
  • Develop functionally equivalent FPGA implementation of analog/mixed signal IP.
  • Develop FPGA based system integrating FPGA IP, 3rd party IP, custom IP, memory IP and other logic blocks.
  • Collaborate with firmware developer and create a flexible register interface to FPGA HW.
  • Collaborate with PCB designer and develop synthesis script/layout strategy to meet frequency target at different board level.
  • Write design specification, test plan, execute and debug FPGA verification and validation.
  • Responsible for understanding design trade-offs that balances functionality, performance, FPGA resource usage – decide on upgrading FPGA platform at the right time of overall product lifecycle.
  • Participate in continuous improvement process and leverage the capabilities of the latest FPGA technology to ensure quality and faster time to market.


Requirements

  • Bachelor’s degree in Electronic/Electrical Engineering, Computer Engineering or Computer Science with at least 7 years of experience (Master’s degree is preferred).
  • In-depth understanding and prior FPGA design project with AHB or AXI interconnect protocol.
  • In-depth understanding and prior FPGA design project with serial, SDR, DDR IO interface at high frequency.
  • In-depth understanding and prior FPGA or ASIC design project with Flash or DRAM memory controller.
  • In-depth understanding and prior FPGA SoC design project using Xilinx or Altera FPGA.
  • Able to create HW architecture from algorithm specification and/or design requirement specification.
  • Able to write synthesizable RTL, integrate hard IP, Soft IP and create FPGA based SoC.
  • Able to create test bench for HW and SW system level simulation.
  • Able to maximize use of FPGA library for high speed interface design with delay elements and calibration.
  • Able to optimize design or synthesis constraints to achieve timing closure.
  • Able to write RTL using Verilog/System Verilog.
  • Experience with design methodology tools such as Vivado, Questa, Code link, Oscilloscope, Logic Analyzer.
  • Must have strong teamwork characteristics and good communication skills.
  • Able to work independently and can proactively learn new skillset and knowledge.
  • Priority will be given to candidates who are fluent with scripting language such as Python, Tcl; with C-Language and familiar with the Linux platform.